Planar capacitors, typically used in embedded printed wiring boards, are commonly made from a dielectric binder having dispersed therein, a ferroelectric filler. These binders can typically include polyimides, epoxy, acrylics, or fiberglass reinforced materials. These planar capacitors can be produced as a thin film, or these composites can be cast in their liquid form onto a metal foil and then cured.
A ‘subtractive process’ is typically employed to form electrodes or circuit traces on a planar capacitor-metal laminate. The metal layer is converted to a metal pattern by chemically etching most of the metal material and using the planar capacitor layer as a support layer. However, such metal subtraction processes can be expensive, environmentally unfriendly, and increasingly problematic when attempting to meet increasingly difficult industry performance requirements.
U.S. Pat. No. 5,870,274 to Lucas, is directed to a method of forming a bypass capacitor element within a printed circuit board (PCB). The process includes the steps of arranging one or more uncured dielectric sheets with conductive foils on opposite sides, and laminating the conductive foils to the dielectric sheet as the PCB is formed by a final lamination step.
EP 1 367 872 A2 to Goosey et al., is directed to a laser activated dielectric material and an electroless deposition process, involving a sensitizing pre-dip step and a milling step (for incorporating titanium dioxide, aluminum nitride or zirconium dioxide filler into the dielectric coating material) and then ultimately converting the filler (using laser energy) into a metallization catalyst (i.e., an area that can receive metal via electroless and/or electrolytic metal deposition).